ADP5042
Data Sheet
Rev. A | Page 18 of 32
THEORY OF OPERATION
ENABLE
AND MODE
CONTROL
LDO1
CONTROL
SOFT START
PWM/
PSM
CONTROL
BUCK1
DRIVER
AND
ANTISHOOT
THROUGH
OSCILLATOR
V
REF
THERMAL
SHUTDOWN
SYSTEM
UNDERVOLTAGE
LOCK OUT
RESET
GENERATOR
DEBOUNCE
PWM
COMP
VDDA
VDDA
VDDA
GM ERROR
AMP
PSM
COMP
LOW
CURRENT
I
LIMIT
R1
R2
ADP5042
VOUT1
WMOD
ENWD1
ENWD2
VIN1
AVIN
SW
GND
EN1
ENBK
ENLDO1
ENLDO2
ODE
MODE
EN2
EN3
SEL
OPMODE_FUSES
VIN2
AGND VOUT2 VIN3
LDO2
CONTROL
R3
R4
ENLDO1
500&
ENBK
60&
ENLDO2
500&
D
C
B
Y
A
VDDA
R0
R1
MR
WDI1
200k&
VDDA
52k&
40k&
WATCHDOG
DETECTOR1
WATCHDOG
STATUS
MONITOR
WDI2
WATCHDOG
DETECTOR2
POFF
POFF
VOUT3
nRSTO
WSTAT
Figure 56. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5042 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc convertor, two low
dropout linear regulators (LDOs), and a supervisory circuit, with
dual watchdog, for processor control. The regulators are activated
by a logic level high applied to the respective EN pin. The EN1
controls the buck regulator, the EN2 controls LDO1, and the
EN3 controls LDO2. The ADP5042 has factory programmed
output voltages and reset voltage threshold. Other features
available in this device are the mode pin to control the buck
switching operation, a status pin informing the external processor
which watchdog caused a reset and push-button reset input.
When a regulator is turned on, the output voltage is controlled
through a soft start circuit to avoid a large inrush current due to
the discharged output capacitors.
The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition is a function of
the current load and the output capacitor value. This operating
mode reduces the switching and quiescent current losses.
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